module sys_reset_ctrl(
    input  wire sclkin,
    output wire resetb
    );

reg  [25:0] reset_count = 26'h00;                

always@(posedge sclkin)
    if (reset_count[25] == 1'b0)
        reset_count<=reset_count+1'b1;        

assign resetb = reset_count[25];

endmodule
